1. Field of Invention
This invention relates, in general, to a means for communication between integrated circuits of the LSI or VLSI type, and, in particular, to intercommunication between CML gates.
2. Prior Art
FIG. 1 shows a typical arrangement of TTL output logic gates connected on a bus structure with the outputs of various gates connected directly output-to-output. Typically, a TTL output circuit can be operated in a high impedence mode so that there is little or no problem in matching impedances when a plurality of outputs are connected together along a common bus.
FIG. 2 illustrates a typical CML output gate comprising a pair of NPN transistors Q1 and Q2 whose emitters are connected in common to a regulated current source with their collectors coupled to a voltage source through a pair of output resistors. The output from the gate is connected between one of the collectors of one of the transistors and one of the output resistors. The base of transistor Q1 forms the gate input and the base of transistor Q2 is connected to a threshold voltage source at a voltage selected to be approximately halfway between the voltage swing of the digital signal (HIGH and LOW) applied to the base input of the transistor Q1, so that current will alternately flow through transistor Q1 or Q2, which, of course, causes the output voltage to go HIGH or LOW according to the voltage drop across the output resistor. Typically, the voltage swing at the output of the gates is 400 mV, with the resistors being 40 ohms and the regulated current source being 10 mA.
Thus, the output of a typical CML gate depends upon the voltage drop across an output resister, a passive component, which is a function of the regulated current source within the chip. The match between the current source and the output resistance for the proper voltage swing on the output of the gate is critical but is within the limitations of IC processing. However, when attempting to connect CML chips to a bus similar to a TTL system, the parallel effect of the output impedances of the CML output devices would result in a reduction of voltage swing. For example, if A and B are connected in parallel as in a bus, the voltage swing at the outputs would be reduced by one-half; three gates would reduce the voltage swing of the output resistors by two thirds; ten gates would reduce the impedence to 4 ohms, etc. It is conceivable that an external resistance could be used for the output gate voltage swing in place of the 40 ohm impedance of each individual device. However, the lack of tracking in the tolerance value between the external resistance and internal current source value of the CML devices may create a saturation and impedance matching problem.
It is clear, therefore, that the outputs of a typical CML output gate cannot be readily connected to a bus, output-to-output as a TTL system, for inter-chip communication because of an impedance matching problem. Thus, for inter-chip communication between CML gates, a multiplexing arrangement, sometimes called a cross-point or cross-bar switch, is provided which contains suitable logic and is responsive to signals applied to its input for connecting, for example, chip A to chip B, chip A to chip C, etc.
This, of course, not only requires additional controls to operate the cross-point switch, but is necessarily large since two pins are required for each gate coupled thereto, as well as pins for connecting the controls to operate the switch. It is apparent, therefore, that the elimination of the cross-point switch and the ability to connect CML chips directly output-to-input for inter-chip communication is a substantial advantage.
It is, therefore, a first object of this invention to provide a system by which CML output gates may be connected for inter-chip communication, eliminating the cross-point switching network now utilized in the CML environment for inter-chip communication.